Junior FPGA Engineer (VHDL/Verilog)
Astrape Networks is seeking a Jr. FPGA Engineer to design and optimize high-performance networking solutions for AI-driven data centers. Join a cutting-edge deep-tech company and help shape the future of next-generation SmartNICs and network switches.
LOCATION
Schelle (BE)
EMPLOYMENT TYPE
Full-time
What You’ll Do
As a Junior FPGA Engineer, you will design, implement and optimize FPGA architectures for SmartNICs and optical switches using VHDL/Verilog. You will develop and verify designs through simulation and testing in a Python-based environment, integrate IP cores and perform timing analysis and on-target verification. Working closely with the software and networking teams, you will help ensure seamless system integration and high-performance networking solutions.
Key Responsibilities
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Design, implement and optimize FPGA architectures for SmartNICs and optical switches using VHDL/Verilog.
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Develop and verify designs through simulation and testing in a Python-based environment.
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Integrate IP cores into FPGA projects and perform timing analysis and on-target verification.
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Collaborate with the software and networking teams to ensure seamless hardware-software integration.
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Participate in system-level performance testing, debugging and optimization.
Who You are
You are a motivated and detail-oriented FPGA engineer with a passion for networking hardware and high-performance computing. You have a strong foundation in VHDL/Verilog, a problem-solving mindset and an eagerness to learn cutting-edge FPGA technologies. You thrive in a collaborative, fast-paced environment and are excited to contribute to next-generation networking solutions.
At Astrape Networks, you will work on pioneering FPGA-based networking solutions that push the limits of AI-driven data center performance. You will collaborate with industry experts, gain hands-on experience with state-of-the-art technologies and have the opportunity to grow your career in a fast-paced, innovation-driven environment.